document number: mma1210 rev 6, 09/2011 freescale semiconductor data sheet: technical data ? freescale semiconductor, in c., 2011. all rights reserved. surface mount micromachined accelerometer the mma series of silicon capacitive, micromachined accelerometers feature signal conditioning, a 4-pole low pass filter and temperature compensation. zero-g offset full scale span and filter cutoff are factory set and require no external devices. a full system self-test capability verifies system functionality. features ? integral signal conditioning ? linear output ? ratiometric performance ? 4th order bessel filter preserves pulse shape integrity ? calibrated self-test ? low voltage detect, clock monitor, and eprom parity check status ? transducer hermetically sealed at wafer level for superior reliability ? robust design, high shocks survivability ? qualified aecq100, rev. f grade 2 (-40 c/+105 c) typical applications ? vibration monitoring and recording ? impact monitoring ordering information device name temperature range case no. package mma1210eg ? 40 to 125 c 475-01 soic-16 mma1210egr2 ? 40 to 125 c 475-01 soic-16, tape & reel MMA1210KEG ? 40 to 125 c 475-01 soic-16 MMA1210KEGr2 ? 40 to 125 c 475-01 soic-16, tape & reel ?k? suffix indicates device manufactur ed with an alternate silicon sourcing. mma1210 16-lead soic pb-free case 475-01 n/c n/c n/c st v out status v ss v dd n/c n/c n/c n/c n/c n/c n/c n/c 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view pin connections
mma1210 sensors 2 freescale semiconductor figure 1 simplified acceleromet er functional block diagram electro static discharge (esd) warning: this device is sensitive to electrostatic discharge. although the freescale accelerometers contain internal 2 kv esd protection circuitry, extra precaution must be taken by the user to protect the chip from esd. a charge of over 2000 volts can accumulate on the human body or associated test equipment. a charge of this magnitude can alter the performance or cause failure of the chip. when handling the accelerometer, proper esd precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance. table 1. maximum ratings (maximum ratings are the limits to which the devic e can be exposed without c ausing permanent damage.) rating symbol value unit powered acceleration (all axes) g pd 1500 g unpowered acceleration (all axes) g upd 2000 g supply voltage v dd ?0.3 to +7.0 v drop test (1) 1. dropped onto concrete surface from any axis. d drop 1.2 m storage temperature range t stg ?40 to +125 c g-cell sensor integrator gain filter temp comp s elf-test control logic & eprom trim circuits clock generator oscillator v dd v out v ss st status
mma1210 sensors freescale semiconductor 3 table 2. operating characteristics (unless otherwise noted: ?40c t a +105c, 4.75 v dd 5.25, acceleration = 0g, loaded output. (1) ) 1. for a loaded output the measurements are observed after an rc filter consisting of a 1 k resistor and a 0.01 f capacitor to ground. characteristic symbol min typ max unit operating range (2) supply voltage (3) supply current operating temperature range acceleration range 2. these limits define the range of operation fo r which the part will meet specification. 3. within the supply range of 4.75 and 5.25 volts, the device operat es as a fully calibrated linear accelerometer. beyond these supply limits the device may operate as a linear device but is not guaranteed to be in calibration. v dd i dd t a g fs 4.75 3.0 ?40 ? 5.00 ? ? 112.5 5.25 6.0 +125 ? v ma c g output signal zero g (t a = 25c, v dd = 5.0 v) (4) zero g sensitivity (t a = 25c, v dd = 5.0 v) (5) sensitivity bandwidth response nonlinearity 4. the device can measure both + and ? acceleration. with no input acceleration the output is at midsupply. for pos itive acceleration the output will increase above v dd /2 and for negative acceleration the output will decrease below v dd /2. 5. the device is calibrated at 35g. v off v off,v s s v f ?3db nl out 2.35 0.46 v dd 19 3.72 360 ?1.0 2.5 0.50 v dd 20.0 4.0 400 ? 2.65 0.54 v dd 21 4.28 440 1.0 v v mv/g mv/g/v hz % fso noise rms (0.1?1 khz) power spectral density clock noise (without rc load on output) (6) 6. at clock frequency ? 70 khz. n rms n psd n clk ? ? ? ? 110 2.0 2.8 ? ? mvrms v/(hz 1/2 ) mvpk self-test output response (7) input low input high input loading (8) response time (9) 7. v off calculated with typical sensitivity. 8. the digital input pin has an inte rnal pull-down current source to prevent inadvertent self test initiation due to external bo ard level leakages. 9. time for the output to reach 90% of its final value after a self-test is initiated. g st v il v ih i in t st 55 v ss 0.7 v dd ?30 ? 75 ? ? ?100 2.0 93 0.3 v dd v dd ?260 10 g v v a ms status (10), (11) output low (i load = 100 a) output high (i load = 100 a) 10. the status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. the status pin is high whenever the self-test input is high, as a means to check the connec tivity of the self-test and status pins in the applica tion. 11. the status pin output latches high if a low voltage detection or clock frequency failure occu rs, or the eprom parity changes to odd. the status pin can be reset low if the self-test pi n is pulsed with a high input for at least 100 s, unless a fault conditi on continues to exist. v ol v oh ? v dd ? 0.8 ? ? 0.4 ? v v minimum supply voltage (lvd trip) v lvd 2.7 3.25 4.0 v clock monitor fail detection frequency f min 50 ? 260 khz output stage performance electrical saturati on recovery time (12) full scale output range (i out = 200 a) capacitive load drive (13) output impedance 12. time for amplifiers to recover after an acceleration signal causes them to saturate. 13. preserves phase margin (60) to guarantee output amplifier stability. t delay v fso c l z o ? 0.25 ? ? 0.2 ? ? 300 ? v dd ?0.25 100 ? ms v pf mechanical characteristics transverse sensitivity (14) package resonance 14. a measure of the device's ability to reject an accele ration applied 90 from the true axis of sensitivity. v xz,yz f pkg ? ? ? 10 5.0 ? % fso khz
mma1210 sensors 4 freescale semiconductor principle of operation the freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. the device consists of a surface micromachined capacitive sensing cell (g-cell) and a cmos signal conditioning asic contained in a single integrated circuit package. the sensing element is sealed hermetically at the wafer level using a bulk micromachined ?cap'' wafer. the g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). it can be modeled as two stationary plates with a mo veable plate in-between. the center plate can be deflected from its rest position by subjecting the system to an acceleration ( figure 3 ). when the center plate deflects, the distance from it to one fixed plate will increase by the same amount that the distance to the other plate decreases. the change in distance is a measure of acceleration. the g-cell plates form two back-to-back capacitors ( figure 4 ). as the center plate moves with acceleration, the distance between the plates changes and each capacitor's value will change, (c = a /d). where a is the area of the plate, is the dielectric constant, and d is the distance between the plates. the cmos asic uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. the asic also signal conditions and filters (switched capacitor) the signal, providing a high level output voltage that is ratiometric and proportional to acceleration. special features filtering the freescale accelerometers contain an onboard 4-pole switched capacitor filter. a bessel implementation is used because it provides a maximally flat delay response (linear phase) thus preserving pulse shape integrity. because the filter is realized using switc hed capacitor techniques, there is no requirement for external passive components (resistors and capacitors) to set the cutoff frequency. self-test the sensor provides a self-t est feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. this feature is critical in applicat ions such as automotive airbag systems where system integrity mu st be ensured over the life of the vehicle. a fourth ?plate'' is used in the g-cell as a self- test plate. when the user applies a logic high input to the self- test pin, a calibrated potential is applied across the self-test plate and the moveable plate. the resulting electrostatic force causes the center plate to deflect. the resultant deflection is measured by the accelerometer's control asic and a proportional output voltage results. this procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. status freescale accelerometers incl ude fault detection circuitry and a fault latch. the status pi n is an output from the fault latch, or'd with self-test, and is set high whenever the following event occurs: ? parity of the eprom bits becomes odd in number. the fault latch can be reset by a rising edge on the self-test input pin, unless one (or more) of the fault conditions continues to exist. acceleration figure 3. transducer physical model figure 4. equivalent circuit model f e 1 2 -- - a v 2 d 2 ------ = ?? ?? ??
mma1210 sensors freescale semiconductor 5 basic connections pinout description figure 5. soic accelerometer with recommended connection diagram pcb layout figure 6. recommended pcb layout for interfacing accelerometer to microcontroller notes: 1. use a 0.1 f capacitor on v dd to decouple the power source. 2. physical coupling distance of the accelerometer to the microcontroller should be minimal. 3. place a ground plane beneath the accelerometer to reduce noise, the ground plane should be attached to all of the open ended terminals shown in figure 6 . 4. use an rc filter of 1 k and 0.01 f on the output of the accelerometer to minimi ze clock noise (from the switched capacitor filter circuit). 5. pcb layout of power and ground should not couple power supply noise. 6. accelerometer and microcontroller should not be a high current path. 7. a/d sampling rate and any external power supply switching frequency should be selected such that they do not interfere with the internal accelerometer sampling frequency. this will prevent aliasing errors. table 3. pin descriptions pin no. pin name description 1 thru 3 ? leave unconnected. 4 st logic input pin used to initiate self-test. 5 v out output voltage of the accelerometer. 6 status logic output pin to indicate fault. 7 v ss the power supply ground. 8 v dd the power supply input. 9 thru 13 trim pins used for factory trim. leave unconnected. 14 thru 16 ? no internal connection. leave unconnected. n/c n/c n/c st v out status v ss v dd n/c n/c n/c n/c n/c n/c n/c n/c 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 logic input 4 mma1210 st v out output signal r1 1 k 5 c2 0.01 f 7 v dd c1 0.1 f 6 status 8 v dd v ss p0 a/d in v rh v ss v dd st v out v ss v dd 0.01 f 1 k 0.1 f 0.1 f power supply 0.1 f p1 status microcontroller accelerometer c c c c r
mma1210 sensors 6 freescale semiconductor acceleration of the package in the + z direction (center plate moves in the ? z direction) will result in an increase in the output. + z ? z side view activation of self test moves the center plate in the ? z direction, resulting in an increase in the output. 1. when positioned as shown, the earth's grav ity will result in a positive 1g output. direction of earth's gravity field (1) side view dynamic acceleration sensing direction static acceleration sensing direction
mma1210 sensors freescale semiconductor 7 minimum recommended footprint fo r surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. with the correct footprint, the packages will self-align when subjected to a solder reflow process. it is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads. figure 7. footprint soic-16 (case 475-01) 0.380 in. 9.65 mm 0.050 in. 1.27 mm 0.024 in. 0.610 mm 0.080 in. 2.03 mm
sensors 8 freescale semiconductor mma1210 package dimensions page 1 of 2 case 475-01 issue c 16 lead soic
sensors freescale semiconductor 9 mma1210 package dimensions page 2 of 2 case 475-01 issue c 16 lead soic
mma1210 rev. 6 09/2011 rohs-compliant and/or pb-free versions of freesca le products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http:/www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconduc tor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discla ims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsid iaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are tradem arks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc. 2011. all rights reserved.
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